The present invention relates to semiconductor integrated circuits, and more particularly to neural network devices that have increased on-chip functionality and yet need fewer package pins.
A zero instruction set computer (ZISC) chip based on neural networks was developed by IBM in Paris and the present inventor, Guy Paillet. The first generation ZISC chip has thirty-six independent neurons or parallel processors, e.g., ZISC-036. Each cell includes sixty-four bytes storage, a distance evaluator and a category register. Vectors that enter the chip are broadcast to all the cells for evaluation of the distance, or similarity, between the incoming vector and stored vectors. If the input and stored vectors match, or are similar, the category or attribute register will output to the response bus. Each of these cells is designed to compare an input vector of up to sixty-four bytes with a similar vector stored in the cell""s memory. If the input vector matches the vector in the memory near enough, the neuron cell xe2x80x9cfiresxe2x80x9d its output. Otherwise, it doesn""t. All thirty-six cells in a ZISC chip compare their memory to the input vector at the same time. The cells that had a match are identified at the output. The ZISC will learn new vectors and adapt to the collection of reference vectors by submitting the training vector along with the desired output. No programming is required to teach the network. Save and restore operations allow transfer to and from the host computer.
In prior art recognition systems, a serial approach is usually used for pattern matching, e.g., a computer program loads a pattern into a memory, then fetches stored patterns from a large array, and then compares them one at a time looking for matches. More patterns to check means more time is needed to do the checking. Very fast computers can check lots of patterns in a short time, but eventually, a limit is reached in how many patterns can be realistically processed. A ZISC network, such as one comprised of ZISC036 devices, matches all the patterns in memory with the input at one time. The number of patterns in memory can be expanded by adding more such devices, and without suffering a decrease in recognition speed. Conventional ZISC chips have been used to offload the recognition function from general-purpose computers in various applications.
As data is input in the form of vectors to arrays of neural networks, one or more of the neurons will xe2x80x9cfirexe2x80x9d. It can be important in many applications to know which particular neuron had the closest of all matches. But in anything other than small arrays, having to resort to a sequential search for that closest-matching neuron is not practical. So the present inventor, Guy Paillet, and IBM describe a search and sort circuit and method useful in IBM ZISC-036 neural networks in U.S. Pat. No. 5,740,326, issued Apr. 14, 1998. Such Patent is incorporated herein by reference.
U.S. Pat. No. 5,740,326, describes using a bus of fourteen, for example, open-collector lines on which all neurons impress their xe2x80x9cdistancexe2x80x9d in digital binary format. Each neuron snoops back such bus to see if the distance it has written out in parallel with all the other neuron distances is the smallest. If the distance written out equals the distance snooped back in, then that neural network has the closest distance of all. In practice, rounds of elimination are used, e.g., one round for each of the fourteen open-collector wires. The eliminations start with the most significant bits and work down wire-by-wire to the least significant bit. So a fourteen-bit binary distance will require fourteen cycles of search and sort.
A principle drawback of implementing such scheme in an integrated circuit is that fourteen (or more) package pins are needed on each ZISC device to support the open-collector bus and another fourteen (or more) are needed for the snoop input. So thirty-two package pins are needed in practical applications to support the search and sort mechanism of U.S. Pat. No. 5,740,326.
It is therefore an object of the present invention to provide a neural network integrated circuit that implements a search-and-sort function.
It is a further object of the present invention to provide a neural network integrated circuit that reduces the number of package pins needed over conventional devices.
Briefly, a neural network integrated circuit embodiment of the present invention comprises a neuron circuit with a distance register that is compared in a competition for the closest-hit with other neurons. The closest-hit comparison is conducted bit-by-bit over the many bit positions of a distance measure in binary format. A single-wire AND-bus interconnects every neuron within a chip and across multiple chips. Each neuron drives the single-wire AND-bus with an open-collector buffer. All neurons press the single-wire AND-bus with their respective distance measures in successive cycles, starting with the most significant bit. For example, a fourteen-bit binary distance word requires fourteen comparison cycles. Any neuron that sees a xe2x80x9c0xe2x80x9d on the single-wire AND-bus when its own corresponding bit in its distance measure is a xe2x80x9c1xe2x80x9d, automatically drops from the competition. By the time the least significant bit is compared, a single closest distance will have been determined. Such neuron that wins announces itself with an identifying code.
An advantage of the present invention is that a neural network integrated circuit is provided that cooperates with other such devices to search and sort out which is closest in training to a particular test vector.
Another advantage of the present invention is that a neural network integrated circuit is provided that provides hit counter information.
A further advantage of the present invention is that a neural network integrated circuit is provided that reduces the package pin count, e.g., from 144-pins to 64-pins.
These and other objects and advantages of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiments which are illustrated in the various drawing figures.